In (for instance embedded) multi-processor computing systems, it is a common task to exchange data between processors (Central Processing Units, CPU). Especially when the CPUs reside on different ASICs (Application Specific Integrated Circuit) this is not a trivial task. An ASIC may denote a “System on Chip” comprising a CPU, busses, hardware accelerators and interfaces on one single chip. In contrast to an FPGA (Field Programmable Gate Array) which can be denoted as a reprogrammable variant of an ASIC which may be used in prototypes, an ASIC can not simply be reprogrammed but is fixed after production.
A FIFO (First In First Out) may denote a special kind of buffer. Data words written to this buffer are queued up in the order they are written. Reading from this buffer returns the data words in the same order they were written and at the same time removes them from the buffer. Data management based on a FIFO architecture has the advantages that it decouples different clock domains, and that a full length can be used with an arbitrary combination of small and big data sections. Furthermore, it may be advantageous that the FIFO can be written while it is read at the same time. A shortcoming of the FIFO architecture is that every read access has an irreversible impact. For instance, it is not possible to just read a header and to decide to not process this data section directly afterwards. The header is already removed from to FIFO and has to be stored in another place to have it available later. Another shortcoming of a conventional FIFO is that it is only possible to access the most front data element in the FIFO.
A “mailbox” may be denoted as a data management architecture in which a sender may input data into a repository such as a memory and operates a kind of button. This terminates access of the sender to the data in the memory and enables access for a recipient to the data in the memory. An advantage of a corresponding data management architecture is the possibility of a random access on all data of the provided repository. Such a data management architecture has however the shortcomings that, if data sections are of different size, the repository must be prepared for the biggest one (smaller data sections waste memory), and that it does not decouple clock domains. Moreover, switching from one repository to another must not happen during a read access and additional synchronization might be needed.
In computing, a shared memory may denote a memory that may be simultaneously accessed by multiple programs or users with the intent to provide communication among them or avoid redundant copies. Depending on context, programs may run on a single processor or on multiple separate processors. Such a data management concept is quite simple and fast. However, reading and writing must be synchronized, for instance a ring buffer might not be read while it is already being overwritten again. Another shortcoming is that the administration of the buffer is shifted to the software, which may be slow and may consume CPU time.
Hence, each of the above mentioned data management architectures has individual shortcomings.